Layout to circuit extraction for three-dimensional thermal-electrical circuit simulation of device structures

In this paper, a method is proposed for extraction of coupled networks from layout information for simulation of electrothermal device behavior. The networks represent a three-dimensional (3-D) device structure with circuit elements. The electrical and thermal characteristics of this circuit representation are calculated with a circuit simulator. Spatial potential distributions, current flows, and temperature distributions in the device structure are calculated on the spatial coordinates. This simulation method can be placed between device simulation and (conventional) circuit simulation. It has been implemented in a circuit simulator and is demonstrated for simulation of self-heating in a bipolar low frequency power transistor. The main advantage of this simulation method is that not only the 3-D thermal behavior of the whole chip is simulated, but that this is also directly coupled to the electrical device behavior by means of the power dissipation and temperature distribution in the device. This offers the possibility for the circuit designer to simulate 3-D, coupled, thermal-electrical problems with a circuit simulator. As an example, the influence of the emitter contacting on the internal temperature and current distribution of a BJT is investigate

A novel approach to sequence validating protein expression clones with automated decision making

<p>Abstract</p> <p>Background</p> <p>Whereas the molecular assembly of protein expression clones is readily automated and routinely accomplished in high throughput, sequence verification of these clones is still largely performed manually, an arduous and time consuming process. The ultimate goal of validation is to determine if a given plasmid clone matches its reference sequence sufficiently to be "acceptable" for use in protein expression experiments. Given the accelerating increase in availability of tens of thousands of unverified clones, there is a strong demand for rapid, efficient and accurate software that automates clone validation.</p> <p>Results</p> <p>We have developed an Automated Clone Evaluation (ACE) system – the first comprehensive, multi-platform, web-based plasmid sequence verification software package. ACE automates the clone verification process by defining each clone sequence as a list of multidimensional discrepancy objects, each describing a difference between the clone and its expected sequence including the resulting polypeptide consequences. To evaluate clones automatically, this list can be compared against user acceptance criteria that specify the allowable number of discrepancies of each type. This strategy allows users to re-evaluate the same set of clones against different acceptance criteria as needed for use in other experiments. ACE manages the entire sequence validation process including contig management, identifying and annotating discrepancies, determining if discrepancies correspond to polymorphisms and clone finishing. Designed to manage thousands of clones simultaneously, ACE maintains a relational database to store information about clones at various completion stages, project processing parameters and acceptance criteria. In a direct comparison, the automated analysis by ACE took less time and was more accurate than a manual analysis of a 93 gene clone set.</p> <p>Conclusion</p> <p>ACE was designed to facilitate high throughput clone sequence verification projects. The software has been used successfully to evaluate more than 55,000 clones at the Harvard Institute of Proteomics. The software dramatically reduced the amount of time and labor required to evaluate clone sequences and decreased the number of missed sequence discrepancies, which commonly occur during manual evaluation. In addition, ACE helped to reduce the number of sequencing reads needed to achieve adequate coverage for making decisions on clones.</p

Fast thermal cycling-enhanced electromigration in power metallization

Multilevel interconnects used in power ICs are susceptible to short circuit failure due to a combination of fast thermal cycling and electromigration stresses. In this paper, we present a study of electromigration-induced extrusion short-circuit failure in a standard two level metallization currently used in power ICs and in particular the effect of fast thermal cycling on the subsequent electromigration lifetime. A special test chip was designed, in which the electromigration test structure is integrated with a heating element and a diode as temperature sensor in order to generate fast temperature swings and to monitor them. Experimental results showed that with the introduction of fast thermal cycling as a preconditioning, the electromigration lifetime is significantly reduced. We observed that the reduction of the electromigration lifetime depends on the stress time, temperature range and the minimum temperature. Electromigration simulations using a two-dimensional simulator confirm the extrusion short circuit as failure mechanism

Electrothermomigration-induced failure in power IC metallization

Metal migration by driving force of electron-flow and temperature gradient is a major reliability concern in power integrated circuits, especially for advanced integrated circuits where there are increasing density of the integrated power components and power dissipation. In this paper, we present a study of the combined effects of electromigration and thermomigration. A special test chip is designed for this study, in which several on-chip heater elements and temperature sensor are realized to impose and measure a temperature gradient, respectively. Our experimental results show that the electromigration lifetimes are much shorter in the presence of a temperature gradient than in a uniform temperature. The shortening of the electromigration lifetimes can be attributed to the effect of temperature gradient on electromigration-induced failure, rather than an additional \ud driving force by thermomigration (due to a temperature gradient). Our observation is in qualitative agreement with recent theoretical model

Fast thermal cycling-enhanced electromigration in power metallization

Fast thermal nterconnects used in power ICs are susceptible to short circuit failure due to a combination of fast thermal cycling and electromigration stresses. In this paper, we present a study of electromigration-induced extrusion short-circuit failure in a standard two level metallization currently used in power ICs and in particular the effect of fast thermal cycling on the subsequent electromigration lifetime. A special test chip was designed, in which the electromigration test structure is integrated with a heating element and a diode as temperature sensor in order to generate fast temperature swings and to monitor them. Experimental results showed that with the introduction of fast thermal cycling as a preconditioning, the electromigration lifetime is significantly reduced. We observed that the reduction of the electromigration lifetime depends on the stress time, temperature range and the minimum temperature. Electromigration simulations using a two-dimensional simulator confirm the extrusion short circuit as failure mechanism. cycling-enhanced electromigration in power metallizatio